Compiler and logic circuit design method

ABSTRACT

A compiler in which pseudo C descriptions ( 1 ) that are capable of describing parallel operations at a statement level and at a cycle precision by clock boundaries and register assignment statements are input, the register assignment statements are identified (S 2 ), so as to generate executable C descriptions ( 3 ), to extract state machines having undergone reductions in the numbers of states, and to decide whether or not a loop to be executed in the 0th cycle is existent (S 5 ), and if the loop is nonexistent, circuit descriptions ( 4 ) that are capable of being logically synthesized are generated. Thus, the pseudo C descriptions in which the clock boundaries are explicitly inserted into the C descriptions are input, and the pseudo C descriptions which permit the register assignment statements to be described in parallel at the statement level are input, so that a pipeline operation attended with a stall operation can be represented.

FIELD OF THE INVENTION

The present invention relates to technology in which programdescriptions for a simulation or circuit descriptions for specifyinghardware are automatically generated from program descriptions. By wayof example, it relates to technology which is effective when applied tothe design of a logic circuit executing a pipeline operation, forexample, a logic circuit such as CPU (Central Processing Unit).

BACKGROUND OF THE INVENTION

There has been technology for generating the circuit descriptions of adigital circuit with a program language. A technique stated in PatentDocument 1 includes a collective assignment part according to whichvariables are classified into ones indicative of registers and onesindicative of the inputs of the registers, whereupon the secondvariables are collectively assigned to the first variables afterprocessing in a module part. A technique stated in Patent Document 2consists in that parts which are sequentially controlled within aprogram descriptive of circuit operations in a universal programlanguage are specified in a specification process part, that thedescriptions of the parts to be sequentially controlled are thereafterconverted so as to operate as state machines, in a conversion processpart and by employing the universal program language, that the programafter the conversion is acquired, that parts which operate in parallelare subsequently extracted from within the converted program in aprogram generation process part, and that a program which accesses allthe extracted parts is generated.

-   -   Patent Document 1: JP-A-2002-49652    -   Patent Document 2: JP-A-10-149382

SUMMARY OF THE INVENTION

The method according to Patent Document 1 includes three constituents;(1) modules which indicate circuit operations, (2) the collectiveassignment part which performs the register assignments, and (3) a looppart which is iterated every clock cycle. It particularly features thatthe register assignments (2) are executed after obtaining the modules(1), within the loop part (3). However, the modules (1) do not containclock boundaries, and the clock boundaries are infallibly contained inthe loop part (3). Therefore, in order to describe a circuit operationwhich extends over a plurality of cycles, the circuit operation needs tobe divided at the clock boundaries. By way of example, it must bedescribed that, when a certain condition has held, a circuit operationis begun at an intermediate position of a circuit operation executed ina preceding cycle, but the method is difficult of making such adescription. It has been found out by the inventors that, especiallywhen a circuit which performs a pipeline operation attended with a stalloperation is described by the method stated in Patent Document 1, acomplicated job might be involved, program descriptions becomingcomplicated.

The method according to Patent Document 2 has four features; (1) thatthe parts to be sequentially processed are identified from within theprogram described in the universal language and are converted intogeneral-purpose program descriptions expressive of state machines, (2)that parallelism at a function level is extracted, (3) that theassociation between a program to be turned into hardware and a softwareprogram to control the former program is automated, and (4) that, informing hardware within the parts to-be-sequentially-processed, partsrequiring a flip-flop and a latch are identified and are converted intothe HDL. However, there is no means for explicitly affording clockboundaries, and descriptions at a cycle precision cannot be directlymade. According to an embodiment of Patent Document 2, the clockboundary is set from a function to another function, and it is difficultto describe, for example, that, when a certain condition has held, acircuit operation is begun at an intermediate position of a circuitoperation executed in a preceding cycle. It has been found out by theinventors that, especially a circuit which performs a pipeline operationattended with a stall operation can be described by the method stated inPatent Document 2, but that a complicated job might be involved, programdescriptions becoming complicated.

An object of the present invention is to provide a compiler which canautomatically generate hardware descriptions from program descriptionsthat explicitly indicate clock boundaries.

Another object of the invention is to provide a compiler which caneasily generate the program descriptions or circuit descriptions of acircuit capable of a pipeline operation attended with a stall operation.

Still another object of the invention is to provide a logic circuitdesign method which can design a circuit capable of a pipeline operationattended with a stall operation.

The above and other objects and novel features of the invention will beclarified from the following description of the specification when readin conjunction with the accompanying drawings.

Typical aspects of the invention disclosed in the present applicationwill be briefly outlined below.

[1] The outline of the present invention will be generally explained.Pseudo C descriptions (1) are input in which parallel operations can bedescribed at a statement level and at a cycle precision by clockboundaries (descriptors $) and register assignment statements(descriptions containing operators=$), the register assignmentstatements are identified (S2) to generate executable C descriptions (3)(S3 and S4), and to extract state machines having undergone reductionsin the numbers of states and to decide whether or not a loop to beexecuted in the 0th cycle is existent (S5), and if the loop isnonexistent, circuit descriptions (4) which can be logically synthesizedare generated (S6).

Owing to the above, the pseudo C descriptions in which the clockboundaries are explicitly inserted into the C descriptions are input,and the pseudo C descriptions which permit the register assignmentstatements to be described in parallel at the statement level are input,so that a pipeline operation attended with a stall operation can berepresented.

The C descriptions which can be compiled by a conventional C compilercan be output on the basis of the pseudo C descriptions. Since thenumbers of states are reduced, the circuit descriptions can be outputwhich are accompanied by state machines in the number of states equalto, at most, (the number of clock boundaries afforded by thedescriptions+1).

Since functions can be designed at the program level without caringabout the state machines, the quantity of descriptions is decreased, sothat the design method contributes, not only to shortening the term of adevelopment, but also to enhancing a quality.

Besides, it is permitted to describe a bus interface circuit and anarbitration circuit which cannot be represented by the generaldescriptions of program level as do not designate the clock boundaries.Especially, since the register assignments are describable, descriptionscan be made in consideration of parallelism at the statement level, anda complicated circuit operation such as the pipeline operation attendedwith the stall operation can be easily described with a smaller quantityof codes than in the C descriptions.

Besides, since the pseudo C descriptions are converted into the Cdescriptions which are compilable by the conventional C compiler, ahigh-speed simulation is realized, and the number of man-hour forverifying functions can be sharply diminished. In the function design,accordingly, sharp diminutions in the number of man-hour are realized inboth the logic design and the logic verification.

A state machine of Mealy type can be generated from the programdescriptions in which the clock boundaries are designated, so that amodel inspection at the program level is possible.

The design method is applicable to the development of, for example, acache controller or a DMA controller of which the cycle precision isrequired and for which a high-level synthetic tool is unsuitable, and itis greatly contributive to shortening the term of the design.

[2] In the first aspect of a compiler according to the presentinvention, a compiler can convert first program descriptions (1)described by diverting a predetermined program language, into circuitdescriptions (4); the first program descriptions containing registerassignment statements (descriptions containing operators=$) and clockboundary descriptions ($) which permit circuit operations to bespecified at a cycle precision; the circuit descriptions specifyinghardware which realizes the circuit operations specified by the firstprogram descriptions, in a predetermined hardware description language.

In the second aspect of the compiler according to the invention, acompiler can convert first program descriptions described by diverting apredetermined program language, into second program descriptions (3)employing a predetermined program language; the first programdescriptions containing register assignment statements (descriptionscontaining operators=$) and clock boundary descriptions ($) which permitcircuit operations to be specified at a cycle precision. The secondprogram descriptions contain transformed assignment statements (13) intowhich the register assignment statements are transformed so as to becapable of referring to states of preceding cycles, and registerassignment description insertion statements (12) which associatevariables of the transformed assignment statements with changes ofregisters attendant upon cycle changes, in correspondence with the clockboundary descriptions.

In the third aspect of the compiler according to the invention, acompiler can convert first program descriptions (1) described bydiverting a predetermined program language, into second programdescriptions (3) employing a predetermined program language, and circuitdescriptions (4). The first program descriptions contain registerassignment statements and clock boundary descriptions which permitcircuit operations to be specified at a cycle precision. The secondprogram descriptions contain transformed assignment statements intowhich the register assignment statements are transformed so as to becapable of referring to states of preceding cycles, and registerassignment description insertion statements which associate variables ofthe transformed assignment statements with changes of registersattendant upon cycle changes, in correspondence with the clock boundarydescriptions. The circuit descriptions specify hardware which is definedby the second program descriptions, in a predetermined hardwaredescription language.

The predetermined program language is, for example, a C language. Thehardware description language is, for example, a description language ofRTL level.

[3] The first aspect of a logic circuit design method according to theinvention comprises the first step (S1) of inputting first programdescriptions (1) which contain register assignment statements(descriptions containing operators=$) and clock boundary descriptions($) that are described by diverting a predetermined program language inorder to define circuit operations on the basis of timingspecifications, and that permit the circuit operations to be specifiedat a cycle precision; and the second step of generating circuitinformation which satisfies the timing specifications, on the basis ofthe first program descriptions.

The second step may include the step of converting the first programdescriptions, and generating as the circuit information, second programdescriptions (3) containing descriptions (13, 12) into which theregister assignment statements are transformed using input variables andoutput variables (S2), and which assign the input variables to theoutput variables in correspondence with the clock boundary descriptions(S4).

The second step may include the step of converting the second programdescriptions, and generating circuit descriptions (4) which serve tospecify hardware satisfying the timing specifications, in apredetermined hardware description language, as the further circuitinformation on the basis of the second program descriptions.

The design method may further comprise the third step of performing asimulation of a circuit to-be-designed by employing the second programdescriptions.

Regarding the second step, it is also possible to separately graspsecond program descriptions (5) containing descriptions (13) into whichthe register assignment statements are transformed using input variablesand output variables (S2), and third program descriptions (3) containingdescriptions (12) which assign the input variables to the outputvariables in correspondence with the clock boundary descriptions (S4).On this occasion, a simulation is performed on the basis of the thirdprogram descriptions by the third step.

[4] The second aspect of the logic circuit design method according tothe invention comprises an input step of inputting first programdescriptions containing register assignment statements and clockboundary descriptions as are described by diverting a predeterminedprogram language in order to define circuit operations on the basis oftiming specifications, and as permit the circuit operations to bespecified at a cycle precision (S1); and a conversion step of generatingsecond program descriptions containing descriptions (13, 12) into whichthe register assignment statements are transformed using input variablesand output variables (S2) and which assign the input variables to theoutput variable in correspondence with the clock boundary descriptions(S4), and being described in the predetermined program language.

The conversion step may well be a step in which, in course of generatinga CFG on the basis of the first program descriptions, it sets clockboundary nodes in the CFG in correspondence with the clock boundarydescriptions, whereupon it inserts the register assignment descriptionsbehind the clock boundary nodes.

The design method may well further comprise an optimization step ofoptimizing codes of the second program descriptions, while a variabletable of respective state transitions is being created by utilizing theCFG.

The design method may well further comprise a “retain” step ofextracting parts in which variables do not change between states withinthe variable table, as parts which need to be retained, and addingdescriptions for assigning the input variables to the output variables,to the extracted parts.

The design method may well further comprise an extraction step ofextracting the codes which constitute state machines, on the basis ofthe variables and arguments of the respective state transitions withinthe variable table having undergone the “retain” step.

The design method may well further comprise the step of generatingcircuit descriptions which describe hardware of a circuit satisfying thecircuit specifications, in a predetermined hardware descriptionlanguage, while reference is being had to the state machine constitutingcodes extracted by the extraction step, and to the second programdescriptions.

Whether or not a loop to be executed in the 0th cycle is existent isdecided for the first program descriptions, and that, when the loop hasbeen decided to be nonexistent, the conversion step is performed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flowchart exemplifying a logic circuit design methodaccording to the present invention;

FIG. 2 is a block diagram showing a circuit example which is to bedesigned by applying the design method in FIG. 1;

FIG. 3 is a timing chart showing the operating specifications of thecircuit in FIG. 2;

FIG. 4 is an explanatory diagram exemplifying the pseudo C program ofthe circuit to-be-designed in FIG. 2;

FIG. 5 is an explanatory diagram showing the descriptions of anadditional variable declaration and the rewritten descriptions ofregister assignment statements as are obtained by a register assignmentstatement identifying process (S2);

FIG. 6 is an explanatory diagram showing one course of a CFG creationprocess based on pseudo C descriptions;

FIG. 7 is an explanatory diagram showing another course of the CFGcreation process based on pseudo C descriptions;

FIG. 8 is an explanatory diagram showing still another course of the CFGcreation process based on pseudo C descriptions;

FIG. 9 is an explanatory diagram showing still another course of the CFGcreation process based on pseudo C descriptions;

FIG. 10 is an explanatory diagram showing still another course of theCFG creation process based on pseudo C descriptions;

FIG. 11 is an explanatory diagram showing still another course of theCFG creation process based on pseudo C descriptions;

FIG. 12 is an explanatory diagram showing still another course of theCFG creation process based on pseudo C descriptions;

FIG. 13 is an explanatory diagram showing still another course of theCFG creation process based on pseudo C descriptions;

FIG. 14 is an explanatory diagram showing still another course of theCFG creation process based on pseudo C descriptions;

FIG. 15 is an explanatory diagram showing still another course of theCFG creation process based on pseudo C descriptions;

FIG. 16 is an explanatory diagram showing still another course of theCFG creation process based on pseudo C descriptions;

FIG. 17 is an explanatory diagram showing still another course of theCFG creation process based on pseudo C descriptions;

FIG. 18 is an explanatory diagram showing still another course of theCFG creation process based on pseudo C descriptions;

FIG. 19 is an explanatory diagram showing still another course of theCFG creation process based on pseudo C descriptions;

FIG. 20 is an explanatory diagram showing still another course of theCFG creation process based on pseudo C descriptions;

FIG. 21 is an explanatory diagram showing the final course of the CFGcreation process based on pseudo C descriptions;

FIG. 22 is an explanatory diagram exemplifying a CFG in whichinformation items on clock boundaries, the start points/end points ofbranches, and the start points/end points of loops are not affixed to aCFG in FIG. 21, for the brevity of description;

FIG. 23 is an explanatory diagram exemplifying a flag insertion statefor the CFG in FIG. 22;

FIG. 24 is an explanatory diagram exemplifying the insertion positionsof register assignment description insertion statements on the CFG;

FIG. 25 is an explanatory diagram exemplifying the first ones ofexecutable converted C descriptions (C program) which have been obtainedvia a C description generation process (S4);

FIG. 26 is an explanatory diagram exemplifying some of the executableconverted C descriptions (C program) succeeding to the descriptions inFIG. 25;

FIG. 27 is an explanatory diagram exemplifying the last ones of theexecutable converted C descriptions (C program) succeeding to thedescriptions in FIG. 26;

FIG. 28 is an explanatory diagram showing the first rule of anumber-of-states reduction process;

FIG. 29 is an explanatory diagram showing the second rule of thenumber-of-states reduction process;

FIG. 30 is an explanatory diagram exemplifying results which have beenobtained by subjecting the CFG in FIG. 22 to the reduction of the numberof states;

FIG. 31 is an explanatory diagram exemplifying a situation where statesare assigned to the CFG subjected to the processes of thenumber-of-states reduction, etc.;

FIG. 32 is an explanatory diagram showing a pseudo C program which is asubject for code optimization, as an example especially simplified forelucidating the process of the code optimization;

FIG. 33 is an explanatory diagram exemplifying a CFG which has beenobtained on the basis of the pseudo C program in FIG. 32;

FIG. 34 is an explanatory diagram exemplifying a situation where statesare assigned to the CFG in FIG. 33;

FIG. 35 is an explanatory diagram exemplifying the initial situation ofa variable table creation process course for state machine generationfor the CFG in FIG. 34;

FIG. 36 is an explanatory diagram exemplifying the next situation of thevariable table creation process course as succeeds to the situation inFIG. 35;

FIG. 37 is an explanatory diagram exemplifying the next situation of thevariable table creation process course as succeeds to the situation inFIG. 36;

FIG. 38 is an explanatory diagram exemplifying the next situation of thevariable table creation process course as succeeds to the situation inFIG. 37;

FIG. 39 is an explanatory diagram exemplifying the next situation of thevariable table creation process course as succeeds to the situation inFIG. 38;

FIG. 40 is an explanatory diagram exemplifying a variable table whichhas been generated via the generation course in FIG. 39;

FIG. 41 is an explanatory diagram exemplifying statements to-be-deletedin redundant statement deletions for the variable table in FIG. 40;

FIG. 42 is an explanatory diagram exemplifying the variable table of aresult which has been obtained by deleting the redundant statements fromFIG. 41;

FIG. 43 is an explanatory diagram showing the result obtained bydeleting the redundant statements, in terms of a CFG;

FIG. 44 is an explanatory diagram exemplifying variables to-be-deletedin local variable deletions for the variable table in FIG. 42;

FIG. 45 is an explanatory diagram showing a result obtained by the localvariable deletion process, in terms of a CFG;

FIG. 46 is an explanatory diagram exemplifying a variable table whichhas been finally updated by performing the redundant statement deletionprocess and the local variable deletion process;

FIG. 47 is an explanatory diagram exemplifying a situation where thedescription of “retain” has been added to a variable table by a “retain”analysis being a later process;

FIG. 48 is an explanatory diagram showing an example in which arithmeticformulae have been further simplified as the optimization of codes, interms of a CFG;

FIG. 49 is an explanatory diagram exemplifying an optimized CFG which isobtained in such a way that the process of code optimization illustratedin FIGS. 32 through 48 by using another example especially simplified isperformed after the state assignment shown in FIG. 31;

FIG. 50 is an explanatory diagram showing a variable table after theoptimization process as corresponds to FIG. 49;

FIG. 51 is an explanatory diagram exemplifying the algorithm of a“retain” analysis;

FIG. 52 is an explanatory diagram showing a variable table whichcorresponds to the result of the “retain” analysis;

FIG. 53 is an explanatory diagram showing a variable table in which theinformation items “retain” in FIG. 52 are overwritten by actual codes;

FIG. 54 is an explanatory diagram showing a state machine extractionprocess in a start state ST0;

FIG. 55 is an explanatory diagram showing a situation where codesconforming to “retain” information items are extracted from a variabletable in correspondence with FIG. 54 and are utilized for the extractionof a state machine;

FIG. 56 is an explanatory diagram showing a state machine extractionprocess in a start state ST1;

FIG. 57 is an explanatory diagram showing a situation where codesconforming to “retain” information items are extracted from a variabletable in correspondence with FIG. 56 and are utilized for the extractionof a state machine;

FIG. 58 is an explanatory diagram showing a state machine extractionprocess in a start state ST2;

FIG. 59 is an explanatory diagram showing a situation where codesconforming to “retain” information items are extracted from a variabletable in correspondence with FIG. 58 and are utilized for the extractionof a state machine;

FIG. 60 is an explanatory diagram showing the first ones of HDLdescriptions which have been generated by an HDL description generationprocess (S6);

FIG. 61 is an explanatory diagram showing ones of the HDL descriptionsas succeed to the descriptions in FIG. 60; and

FIG. 62 is an explanatory diagram showing the last ones of the HDLdescriptions as succeed to the descriptions in FIG. 61.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

<<Outline of Design Method>>

A logic circuit design method according to the present invention isexemplified in FIG. 1. The design method shown in the figure is broadlyclassified into the creation of pseudo C descriptions (pseudo C program)1, and compiler processing 2 for the pseudo C program 1. In the compilerprocessing 2, the pseudo C program 1 is converted into a pseudo Cprogram (stored in a storage section 5) whose transformed assignmentstatement is a register assignment description, and executable Cdescriptions (C program) 3. Besides, the C program 3 is converted intoHDL (Hardware Description Language) descriptions 4 of RTL (RegisterTransfer Level) or the like.

The pseudo C program 1 is a program which includes a clock boundarydescription (also written “clock boundary” simply) capable of specifyinga circuit operation at a cycle precision, and a register assignmentstatement, and which is capable of parallel descriptions at a statementlevel. The expression “pseudo C description” is used in the sense thatit differs from a so-called “native” C language description in which theclock boundary and the register assignment statement are not defined. Itshall not be excluded to base the program language on a high-classlanguage other than the C language.

The compiler processing 2 is performed in such a way that a computerapparatus, not shown, executes a compiler and loads the pseudo C program1. First, the pseudo C program 1 is loaded (S1). The register assignmentstatement is identified for the loaded pseudo C program 1, and theidentified register assignment statement is transformed so as to becapable of referring to the state of a preceding cycle, in other words,it is transformed using an input variable and an output variable (S2).The transformed register assignment statement is also termed the“transformed assignment statement”. The pseudo C program in which theregister assignment statement has been transformed into the transformedassignment statement, is stored in the register information storagesection 5. This pseudo C program in which the register assignmentstatement has been transformed into the transformed assignmentstatement, is fetched from the register information storage section 5,and the control flow graph (hereinbelow, abbreviated to “CFG”) thereofis generated (S3). The generated CFG is stored in an intermediaterepresentation storage section 6. The CFG stored in the intermediaterepresentation storage section 6, and the pseudo C program stored in theregister information storage section 5 are converted into the executableC description program (S4). By way of example, there is inserted aregister assignment description insertion statement which adapts thevariables of the transformed assignment statement to the change of aregister attendant upon a cycle change, in correspondence with the clockboundary description. In other words, there is inserted a registerassignment description insertion statement which assigns the outputvariable of the transformed assignment statement to the input variablethereof in correspondence with the clock boundary description.

In a case where the HDL descriptions 4 are obtained on the basis of thepseudo C program 5, etc., state machines are first generated byinputting them (S5). The state machine generation (S5) is broadlyclassified into a number-of-states reduction process (S5A), theoptimization of a code (S5B), a “retain” analysis for conforming to theHDL descriptions (S5C), and state machine extraction (S5D). Thenumber-of-states reduction process (S5A) and the optimization of thecode (S5B) may well be grasped as processes which belong to the categoryof optimization processing. At the stage of the optimization of the code(S5B), whether or not a loop to be executed in the 0th cycle is existentis decided. If the loop is nonexistent, the “retain” analysis forconforming to the HDL descriptions (S5C), and the state machineextraction (S5D) are performed. In obtaining the C description program,the register assignment description insertion statement may be insertedinto, for example, a clock boundary node. In obtaining the HDLdescription, however, even in a case where a register value does notchange at the clock boundary, this fact needs to be explicitlydescribed. Therefore, the “retain” analysis (S5C) is made. The statemachine to be generated is generated on the basis of a conversion tableof every state transition. The generated state machine is held in astate machine storage section 7. The HDL descriptions 4 are generated onthe basis of such state machines held (S6).

The HDL description 4 are made convertible into logic circuit diagramdata by utilizing a logic synthesis tool. The C descriptions 3 areutilized for the simulation of a logic circuit which is to be logicallysynthesized, and so forth.

Now, the pseudo C program and the compiler processing thereof will bedescribed in detail. The ensuing detailed description will exemplify acircuit design in which specifications in FIG. 3 are fulfilled in acircuit in FIG. 2.

<<Circuit to be Designed>>

Shown in FIG. 2 is a circuit example which is to be designed by applyingthe design method in FIG. 1. A circuit to-be-designed 10 is a pipelineaddition circuit which is attended with a stall operation. The operatingspecifications of the circuit are as follows:

(1) When an input signal valid_a rises, the value of an input signal “a”in a cycle whose signal level has become a high level is accepted. Here,the rise change of the signal valid_a becomes an issue.

(2) When the signal level of an input signal valid_b becomes the highlevel in a cycle next to the rise of the input signal valid_a or in astill later cycle, the value of an input signal “b” in the cycle isaccepted. As to the input signal valid_b, only level detection suffices,and the detection of an edge change is unnecessary.

(3) When the signals “a” and “b” have been accepted by the operations(1) and (2), the added result of the signals “a” and “b” is delivered asan output signal “out” in the next cycle, the signal level of an outputsignal valid_out is brought to the high level in the same cycle, and thesignal level of the output signal valid_out is brought to a low level inthe next cycle.

(4) Unless a new added result is assigned by the operations (1), (2) and(3), the output signal “out” assumes the same value.

(5) The output signal valid_out has its signal level rendered high onlyin the cycle in which the new added result has been assigned to theoutput signal “out” by the operations (1), (2) and (3), and it assumesthe low level else.

FIG. 3 is a timing chart showing the operating specifications of thecircuit in FIG. 2. Referring to FIG. 3, the output data delivery and theinput data acceptance proceed in the identical cycle, so that a pipelineoperation is executed. By way of example, the input of data a2 and theoutput of data a1+b1 are parallelized. Besides, the output data isdelivered in a cycle next to the cycle in which the value of the inputsignal valid_b has become “1”, in or after the cycle next to the rise ofthe input signal valid_a, so that the pipeline operation is attendedwith the stall operation. By way of example, the acceptance of data b2waits for 2 cycles after the acceptance of data b1.

<<Pseudo C Program>>

Exemplified in FIG. 4 is the pseudo C program of the circuitto-be-designed 10. In the descriptions in FIG. 4, numeral 11 indicates acircuit operation description part in which the circuit operation of thecircuit to-be-designed 10 is described. The descriptions of the pseudo Cprogram shown in the figure are as follows:

-   Line 1: Library invocation in C language-   Lines 2-7: Prototype declaration part of Function pipeline-   Lines 8-14: Main function part-   Lines 9-10: Local variable declaration part of Main function, in    which Output signal is declared in Pointer type-   Lines 11-12: Initialization of Local variable of Main function (Only    an output signal is initialized, and especially in a case where a    register is presumed at conversion into an RTL as to the output    signal, an initial value designated here becomes a reset value.)-   Lines 15-36: Pipeline function part-   Lines 18-20: Local variable declaration part of Pipeline function    (Especially in a case where the register is presumed at the    conversion into the RTL as to a local variable, an initial value    designated here becomes a reset value)-   Lines 21-35: Circuit operation description part 11

The details of the circuit operation description part 11 are as follows:

-   Lines 21 and 35: Representation of Circuit by Endless loop-   Line 22: Statement of Register assignment of Input variable valid_a    to Local variable valid_a_tmp (Here, it is designated by    0x0001&valid_a that the effective bit width of the input variable    valid_a is one bit.)-   Line 23: Decision statement as to Whether or Not Input variable    valid_a is 1′b1 and Local variable valid_a_tmp is 1′b0 (That is, a    decision statement as to whether or not the input variable valid_a    rises. Especially, it is designated by 0x0001&valid_a_tmp that the    effective bit width of the local variable valid_a_tmp is one bit.)-   Line 24: Statement of Assignment of Input signal “a” to Local    variable a_tmp (Especially, it is designated by 0x7FFF&a that the    effective bit width of the input variable “a” is 15 bits.)-   Line 25: Clock boundary-   Line 26: Goto label-   Lines 27-28: It is expressed that, if the input variable valid_b is    1′b1, the input variable “b” is assigned to a local variable b_tmp,    and that a branch is caused to a label L astride one clock boundary    else. (Especially, it is expressed by 0x0001&valid_b that the    effective bit width of the input variable “b” is one bit, and by    0x7FFF&b that the effective bit width of the input variable “b” is    15 bits.)-   Line 29: Statement of Register assignment of Sum between Local    variables a_tmp and b_tmp, to Output variable “out”-   Line 30: Statement of Register assignment of Constant 0x0001 to    Output variable valid_out-   Line 31: Expressing Branch in case where Decision of if Statement at    Line 23 has Failed, that is, Branch in case where Input variable    valid_a has not Risen-   Line 32: Clock boundary-   Line 33: Statement of Register assignment of Constant 0x0000 to    Output signal valid_out

Symbol “$” signifies the clock boundary description, and symbol “=$” theregister assignment. They are not the general descriptors or operatorsof the C language. The pseudo C program employing them can be called“program descriptions diverting the C language” in that sense.

As understood from the circuit operation description part 11, theparallel operation can be simply described at a statement level and at acycle precision by the clock boundary descriptions and the registerassignment statements. The “cycle precision” signifies that synchronismwith clock cycles is intended.

There will be explained the descriptive contents of the circuitoperation description part 11 in FIG. 4. The input variable valid_a isassigned to the local variable valid_a_tmp, thereby to decide the riseof the input variable valid_a based on the if statement. In the case ofthe rise, the input signal “a” is accepted into the local variablea_tmp, and whether or not the input signal valid_b is 1′b1 is decided inthe next cycle. If the input signal valid_b is 1′b1, the value of theinput signal “b” is assigned to the local variable b_tmp, and if not,whether or not the input signal valid_b is 1′b1 is decided again in thenext cycle. This is iterated until the input signal valid_b becomes1′b1. This operation corresponds to the stall operation. Here, the sumbetween the local variables a_tmp and b_tmp expresses the sum betweenthe accepted values “a” and “b”, and it is register-assigned to theoutput variable “out”, while at the same time, 1′b1 is register-assignedto the output signal valid_out. Thus, it is represented that theaddition result and the valid_out signal are 1′b1 one cycle after theacceptance of the input signals “a” and “b”. In the case where the inputsignal valid_a has not risen as the result of the rise decision thereofbased on the if statement, 1′b0 is register-assigned to the signalvalid_out one cycle later. The rise of the signal valid_a can occur, atmost, only once in two cycles. Therefore, the signal valid_out becomes1′b1 only when the new assignment to the variable “out” has been done atLine 29, and it becomes 1′b0 else.

The register assignment statement at Line 22 in FIG. 4 supposes aregister being a sequential circuit, in order to specify the operationat the cycle precision, and the left hand (valid_a_tmp) thereof can begrasped as a variable which holds the output of the register, namely,the value of the last cycle. The right hand (0x0001&valid_a) of theregister assignment statement can be grasped as the register input atthe current time. Besides, regarding the register assignment statementscontained at Lines 29 and 30 in FIG. 4, a clock is consumed in the clockboundary description at Line 32 later. Herein, the signal “out” isoutput in the next cycle in accordance with the circuit specificationsin FIGS. 2 and 3. As a result, descriptions at the cycle precision areinfallibly required as to the signals “out” and valid_out, and registerassignment statements are therefore employed for the descriptions.

<<Identification of Register Assignment Statement>>

Next, the register assignment statement identifying process S2 will bedescribed. In the register assignment statement identifying processpart, an assignment statement in which the symbol $ is added betweensymbol=and the right hand is identified, the register assignmentstatement in the circuit operation description part 11 and the type andinitial value of the variable at the left hand of the registerassignment statement are stored, and the identified register assignmentstatement:

-   signal_latched=$ signal    is altered to descriptions:-   signal_latched_i=signal;-   signal_latched=signal_latched_o.

It is possible to grasp signal_latched_i as an input variable as whichan input at the current time is given, and signal_latched_o as an outputvariable as which an output in the last cycle is assigned. The newvariables having developed by the alteration:

-   signal_latched_i, signal_latched_o    are added to the variable declaration part by referring to the type    and initial value of the variable stored before. In case of, for    example:-   unsigned char signal_latched=0x01,    there are added:-   unsigned char signal_latched o=0x01;-   unsigned char signal_latched_i.

Especially in a case where the variable at the left hand of the registerassignment is of the pointer type (to which symbol * is affixed), avariable declaration is done using the pointer type. In case of, forexample:

-   unsigned char *signal_latched,    there are added:-   unsigned char signal_latched_o=0x01;-   unsigned char signal_latched_i.

Especially for the variable to-be-added, a flag variable which is of thesame type and whose initial value is “0” is also stored as such. In caseof this example:

-   unsigned char flg_signal_latched=0x00    is stored as the variable to-be-added. Incidentally, the    descriptions having undergone the above alterations are also stored.    Besides, the initial value of the variable is employed as a reset    value in a case where the register presumption for the variable has    been done at the HDL conversion.

Exemplified in FIG. 5 are the results obtained by the registerassignment statement identifying process S2. The descriptions of anadditional variable declaration and the descriptions of transformedassignment statements (rewritten register assignment statements) 13 havebeen altered as compared with the descriptions of the pseudo C programin FIG. 4.

<<CFG Generation>>

Next, the CFG generation process will be explained. The “CFG” generallysignifies a graph which indicates the flow of a control within eachfunction.

In the CFG generation process, the CFG is created by loading the circuitoperation description part 11. In particular, the process creates theCFG which has nodes for identifying the loops of “while”, “for”, etc.,the conditional branches of “if”, “case”, etc., and label branches tolabels based on goto statements. After all, the process creates the CFGwhich has as its nodes, the loops of “while”, “for”, etc., theconditional branches of “if”, “case”, etc., and the label branches tothe labels based on the goto statements. The CFG is created in such away that individual statements are loaded till the end of the program,and that the nodes are connected by directed sides (sides havingdirections) along the flow of the program while the nodes are beingcreated in accordance with a procedure of steps 1)-7) stated below. Acreation process for the CFG as conforms to the procedure of steps 1)-7)is shown in due course in FIGS. 6 through 21. A loop statement stack, abranch statement stack, and the CFG in the course of the generation areshown in each of the figures.

1) At the start of a loop, the line No. of the loop and a terminalsymbol expressive of the loop, such as “while” or “for”, are registeredin the loop statement stack, a loop start node (NDs) is created, and theline No. and the terminal symbol are affixed to the node. Besides, inthe presence of a “for” or “while” loop end condition, the condition isassigned to a suitable symbol and is affixed to an output branch, andthe affixed condition is stored in a pair with the allotted symbol.

2) At the end of a loop, information lying at the head is taken awayfrom the loop statement stack, a loop end node expressive of the loopend is created, and the line No. and “end of the terminal symbol” of theloop are affixed to the node. However, “continue” or “break” is nothandled as the end of the loop. Besides, in the presence of a “do-while”loop end condition, the condition is assigned to a suitable symbol andis affixed to an output branch, and the affixed condition is stored in apair with the allotted symbol.

3) At the start of a conditional branch, the line No. of the branch anda terminal symbol expressive of the branch, such as “if” or “case”, areregistered in the branch statement stack, a conditional branch startnode is created, and the line No. and the terminal symbol are affixed tothe node. Besides, a branch condition is assigned to a suitable symboland is affixed to an output branch, and the affixed condition is storedin a pair with the allotted symbol.

4) At the end of a conditional branch, information lying at the head istaken away from the branch statement stack, a conditional branch endnode expressive of the conditional branch end is created, and the lineNo. and “end of the terminal symbol” of the branch are affixed to thenode.

5) In case of a label, a label node expressive of the label is created,and the line No. and label symbol of the label are affixed to the node.

6) In case of a clock boundary, a clock boundary node is created, andthe line No. and symbol $ of the clock boundary are affixed to the node.

7) In any case other than the above, a node to which the correspondingline No. and statement are affixed is created, and the node is mergeduntil any of the cases 1)-6) is met.

The CFG is created in accordance with the above procedure of steps. Inthe ensuing description, however, the CFG in which information items onthe clock boundary, the start point/end point of the branch, and thestart point/end point of the loop are not affixed as exemplified in FIG.22 shall be used for the brevity of the description. Especially, onlythe clock boundary node is represented by a black round mark, and theother loop, conditional branch and label branch nodes are represented bywhite round marks.

<<C Description Generation>>

The C description generation process S4 will be explained. In the Cdescription generation process S4, there are inserted a statement whichassigns “1” to a flag variable among the variables stored as thevariables to-be-added in the register assignment statement identifyingprocess, the flag variable lying directly under the part (transformedassignment statement) altered in the register assignment statementidentifying process, and a statement which assigns “0” to a flagvariable lying directly under an assignment statement that is not aregister assignment statement and that is for the variable of the lefthand of the register assignment statement. Simultaneously therewith, thevariable declaration stored in the register assignment statementidentifying part is added to the local variable declaration part. InFIG. 23, the flags of flg_valid_a_tmp=1 and flg_valid_out=1 areinserted.

Subsequently, register assignment description insertion statements aredetermined. Herein, the register assignment description insertionstatements are created for all the variables of the right hand of theregister assignment statement identified in the register assignmentstatement identifying process S2. More specifically, subject to:

-   register assignment statement:-   signal_latched=$ signal;-   altered descriptions:-   signal_latched_i=signal;-   signal_latched=signal_latched_o;    added variables:-   signal_latched_i, signal_latched_o, flg_signal_latched,-   the following descriptions are created:-   signal_latched_o=signal_latched_i;-   if(flg_signal_latched==1) signal_latched=signal_latched_o.

The descriptions are created for all the variables of the right hand ofthe register assignment statement identified in the register assignmentstatement identifying process. In the case of the example, the followingdescriptions are obtained:

-   valid_a_tmp_o=valid_a_tmp_i;-   if(flg_valid_a_tmp==1) valid_a_tmp=valid_a_tmp_o;-   out_o=out_i;-   if(flg_out==1)*out=out_o;-   valid_out_o=valid_out_i;-   if(flg_valid_out==1)*valid_out=valid_out_o.

As exemplified in FIG. 24, the register assignment description insertionstatements are inserted directly under the clock boundary nodes. In FIG.24, reference numerals 12 are given to the register assignmentdescription insertion statements. The conversions into the Cdescriptions thus proceeding may be performed in consideration of theorder of the insertion statements in such a way that the CFG is searchedby executing an algorithm such as depth-first search (DFS) on the basisof the information items of the line Nos. affixed to the individualnodes, etc. Incidentally, comment statements may well be appropriatelyinserted.

Exemplified in FIGS. 25 through 27 is the entirety of the executableconverted C descriptions (C program) 3 which have been obtained via theC description generation process s4.

<<State Machine Generation—Number-of-States Reduction>>

The state machine generation process S5 will be described. Thenumber-of-states reduction process S5A is performed in conformity with,for example, a first or second rule. The first rule of thenumber-of-states reduction process is exemplified in FIG. 28. Morespecifically, there is searched for any of the loop start/end node,conditional branch start/end node and label branch node as has aplurality of input sides, and a graph transformation shown in the figureis performed in a case where at least two of the input sides have clockboundaries. The second rule of the number-of-states reduction process isexemplified in FIG. 29. More specifically, there is searched for thatnode among the loop start/end node, conditional branch start/end nodeand label branch node which has a plurality of output sides, neither aninput signal nor an output signal being contained in conditions affixedto the output sides, and at least two output sides of which have clockboundaries affixed thereto, and a graph transformation shown in thefigure is performed in a case where the clock boundaries of thepreceding stage of the node do not contain the clock boundaries of theoutput sides. Exemplified in FIG. 30 are results which have beenobtained by subjecting the CFG in FIG. 22 to the reduction of the numberof states.

<<State Machine Generation—Code Optimization>>

In the code optimization process S5B, as exemplified in FIG. 31, statesare assigned to the CFG subjected to the processes of thenumber-of-states reduction, etc. According to FIG. 31, an initial stateis assigned to a node on the CFG as corresponds to the start statementof the circuit operation part, and a state is assigned to a clockboundary node on the CFG. However, in a case where only one input sideto the start node exists and where a clock boundary is affixed thereto,the initial state already assigned is deleted. Incidentally, it shoulddesirably be noted that a necessary and sufficient condition for theoccurrence of the initial-state deletion as conforms to the first ruleof the optimization is the existence of only one input side to the startnode and the affixation of the clock boundary thereto. It should also benoted that the number of obtained states infallibly becomes, at most,(the number of clock boundaries described in the circuit operationpart+1).

Here, the process of the code optimization will be described usinganother example especially simplified, with reference to FIGS. 32through 48.

FIG. 32 shows the pseudo C program which is a subject for the codeoptimization. A CFG obtained on the basis of the pseudo C program isexemplified in FIG. 33. Exemplified in FIG. 34 is a situation wherestates are assigned to the CFG in FIG. 33.

FIGS. 35 through 40 exemplify the situation of a variable table creationprocess for the state machine generation, in due course. The creation ofa variable table conforms to the following procedure of steps (1)-(3):(1) Local variables are acquired, (2) the arguments of a function areacquired, and (3) the CFG is traced to a lower level side from anassigned state till arrival at a state, thereby to identify a statetransition and to acquire the information of the definitions andreferences of the variables. When a loop whose both ends are not clockboundaries has been found out at this stage, the detection of azero-cycle loop is decided and is notified to a user, whereupon theprocess is ended. The appearance of the zero-cycle loop signifies that aloop circuit formed of a combinational circuit exists in a circuitto-be-generated, and the existence of the loop circuit signifies that aserious mistake is involved in the circuit to-be-generated. Exemplifiedin FIG. 35 are local variables and arguments in one state transitionfrom a state ST0 to a state ST1. Exemplified in FIG. 36 are localvariables and arguments in another state transition from the state ST0to the state ST1. Exemplified in FIG. 37 are local variables andarguments in a state transition from the state ST0 to a state ST2.Exemplified in FIG. 38 are local variables and arguments in a statetransition from the state ST1 to the state ST0. Exemplified in FIG. 39are local variables and arguments in a state transition from the stateST2 to the state ST0. A variable table exemplified in FIG. 40 isgenerated on the basis of the local variables and the arguments whichhave been obtained in the respective state transitions shown in FIGS. 35through 39. In the descriptions of the variable table in FIG. 40:

-   Def[n] expresses that the variable is defined at Line “n”;-   use@var[m] expresses that the variable is used for an assignment to    a variable “var” at Line “m”;-   pred(cond){ . . . } expresses that { . . . } is performed in a case    where the branch of a condition “cond” has held;-   def[1]use expresses that the variable is used for an assignment to    the variable itself at Line 1; and-   use@pred(cond) expresses that the variable is used in the condition    “cond”.

The optimization process is performed on the basis of, for example, thevariable table in FIG. 40. One aspect of the optimization process is thedeletion of a redundant statement.

As the deletion of the redundant statement, in the first place, in acase where at least two descriptions “def”s exist within the column ofthe state transition for an identical variable, the following processingstep 1) or 2) is executed:

1) A substep 1-1) or 1-2) to be explained below is executed up to thisside of the description “pred(cond){ . . . }” existing posteriorly tothe descriptions “def” (irrespective of the existence or nonexistence ofthe description “pred(cond){ . . . }”). 1-1): In a case where thedescription “def” accompanied by the description “use” does not existposteriorly to the description “def”, only a statement corresponding tothe last description “def” is left. 1-2): In a case where thedescription “def” accompanied by the description “use” existsposteriorly to the description “def”, only the description “def” notaccompanied by the description “use” is left if it exists posteriorly tothe description “def” accompanied by the description “use”, and thedescription “def” accompanied by the description “use” and thedescription “def” anterior to the description “def” accompanied by thedescription “use” are left else. This is iterated until no change comesto occur, and only statements corresponding to the left descriptions“def”s are left.

2) If the description “pred(cond){ . . . }” does not exist posteriorlyto the descriptions “def”s, the processing step is ended, and if itexists, a substep 2-1) or 2-2) to be explained below is executed. 2-1)In a case where the condition of the description “pred(cond){ . . . }”refers to the result of the description “def”, the processing step isended. 2-2) In a case where the condition of the description“pred(cond){ . . . }” does not refer to the result of the description“def”, a branch to the processing step 1) is done.

As the deletion process for the redundant statement, in the secondplace, the variable as to which the description “use” does not exist inany state transition is deleted.

In the redundant statement deletions for the variable table in FIG. 40as based on the above processing procedure, the statements to be deletedare shown in FIG. 41. In this figure, the statements to be deleted areclearly indicated by oblique lines. The variable table of a resultobtained by deleting the redundant statements is exemplified in FIG. 42.The result obtained by deleting the redundant statements is expressed bya CFG in FIG. 43.

Another aspect of the optimization process is the deletion of any localvariable. As the deletion process for the local variable, in the firstplace, each of the following processing steps 1)-3) is executedrightwards sequentially until no change comes to occur, in the statetransition column of each variable:

1) In a case where the description “use” exists posteriorly to thedescription “def” without holding the description “pred(cond){ . . . }”therebetween, a substep 1-1), 1-2), 1-3) or 1-4) is performed. 1-1): Ina case where the description “use” itself is the description “use@pred”,an assignment operation is executed, and the description “def” isdeleted. 1-2): In a case where a variable in the description “@” is thelocal variable and where it is used as the description “use@pred”, anassignment operation is not executed. 1-3): In a case where a variablein the description “@” is a local variable and where it is not used asthe description “use@pred”, an assignment operation is executed, and thedescription “def” is deleted. 1-4): In a case where a variable in thedescription “@” is an argument, an assignment operation is executed, andthe description “def” is deleted.

2) In a case where the description “use” exists posteriorly to thedescription “def” with the description “pred(cond){ . . . }” heldtherebetween, and where a variable used in the condition of thedescription “pred(cond){ . . . }” is an argument, the substeps 1-1)through 1-4) are applied.

3) In a case where the description “use” exists posteriorly to thedescription “def” with the description “pred(cond){ . . . } ” heldtherebetween, and where a variable used in the condition of thedescription “pred(cond){ . . . }” is the local variable, a substep 3-1)or 3-2) is performed. 3-1): In a case where the condition of thedescription “pred(cond){ . . . }” does not refer to the result of thedescription “def”, the substeps 1-1) through 1-4) are applied. 3-2): Ina case where the condition of the description “pred(cond){ . . . }”refers to the result of the description “def”, an assignment operationis not executed.

As the deletion process for the local variable, in the second place, thevariable as to which the description “def” does not exist in any statetransition is deleted, and a CFG after an assignment operation isanalyzed again, thereby to update a variable table.

The variables to be deleted in the local variable deletions for thevariable table in FIG. 42 are shown in FIG. 44. In this figure, thevariables to be deleted are clearly indicated by oblique lines. A resultobtained by the local variable deletion process is expressed as a CFG inFIG. 45.

Exemplified in FIG. 46 is a variable table which has been finallyupdated by performing the redundant statement deletion process and thelocal variable deletion process. The required local variables aremanaged by the variable table. Referring to FIG. 46, it can beidentified that the output variable and the local variable need to beretained in a part where the variable “def” does not exist. The reasontherefor is that the output variable and the local variable mustnaturally be retained in the transition of the states. Accordingly, thenecessity for the “retain” operation in that part becomes easilyidentifiable. As exemplified in FIG. 47, a description “retain” is addedin the corresponding part by a “retain” analysis being a later process.

As the optimization of codes, the simplification of arithmetic formulaeas exemplified in FIG. 48 is further performed.

<<State Machine Generation—Retain Analysis>>

Now, the description shall refer again to the example of the circuitdesign which satisfies the specifications in FIGS. 2 and 3. In FIGS. 32through 48, the process of the code optimization has been illustratedusing the other example which has been especially simplified. After thestate assignment shown in FIG. 31, a similar optimization process isperformed, whereby a CFG after the optimization as shown in FIG. 49 canbe obtained, and a variable table as shown in FIG. 50 can be obtained.The description “retain” is not explicitly indicated in the variabletable in FIG. 50 after the optimization process. It is acquired by a“retain” analysis to be explained below.

The algorithm of the “retain” analysis is exemplified in FIG. 51.Regarding the “retain” analysis, in a case where the description “def”does not exist for the output variable or the local variable at all inthe column of the state transition, this output variable or localvariable needs to be retained in the state transition. Besides, in acase where the description “pred( )” is affixed even in the existence ofthe description “def”, a diagram as shown in FIG. 51 is created for thestate transitions of individual output variables and local variables, soas to identify a part which requires the “retain” operation in a branchbased on the description “pred( )”. Especially for the local variableswhich have been added anew by the register assignment statementidentifying process, if the “retain” operation is required is analyzedfor only the variables which bear information “_i”. Besides, even whenthe information “pred( )” does not exist in the variable table, it isaffixed if necessary, by analyzing the CFG again.

The diagram shown in FIG. 51 is created by creating a tree which has thenodes of the descriptions “use”, “def” etc. with the condition of thedescription “pred( )” as the branch. Besides, a partial tree which islower in level than the description “def” of the tree is deleted, andthat node except the highest-level node as to which the description“def” does not exist in the lower-level nodes thereof is identified as anode which needs to be retained.

Here, the “highest-level node” signifies all of nodes to the node of thedescription “def” or “use” at the shortest distance from the root of thetree, and the brother nodes thereof.

In a case, for example, where the information of the variable “var” inthe state transition STn−>STm as based on a variable table ispred(cond_(—)0){pred(cond_(—)1){use@var_(—)1} [j],pred(cond_(—)2){def[k], pred(cond_(—)3){def[s]}}}, the diagram becomesas shown in FIG. 51.

Exemplified in FIG. 52 is a variable table which corresponds to theresult of the “retain” analysis. The descriptions “retain” are added tothe parts which need to be retained.

Actual codes which are to be added to the parts “retain” in the variabletable can be acquired from the variable table. More specifically, in aprocess for information acquisition from the variable table of the“retain” analysis result, output variables and local variables as towhich the information “retain” is inserted in the columns of thevariable table are acquired. By way of example:

-   -   1) in case of a variable at the left hand of the register        assignment statement, a variable name is stored as sig=sig_o;    -   2) in case of a variable which has been added in the register        assignment statement identifying part and which bears the        information “_i”, a variable name is stored as sig_i=sig_o; and    -   3) in case of any other variable, a variable name is stored as        nxt_sig=sig.        Especially in a case where the description “pred( )” is affixed        to the information “retain”, for example, in a case where the        variable corresponds to the case 3) and where the variable name        is “sig” as        inpred(cond_(—)0){pred(cond_(—)1){pred(!cond_(—)2){retain}}},        this variable is stored as        pred(cond_(—)0){pred(cond_(—)1){pred(!cond_(—)2){nxt_sig=sig}}}.        The above information is overwritten and registered in the        variable table. Exemplified in FIG. 53 is a variable table in        which the information items “retain” have been overwritten by        the actual codes. Further, a variable bearing information “nxt_”        as in “nxt_sig” is stored. In case of the example in FIG. 53,        the variable bearing the information “nxt_” is only a variable        “a_tmp”.

<<State Machine Generation—State Machine Extraction>>

Next, the state machine extraction process S5D will be described. In thestate machine extraction process S5D, search is made by the depth-firstsearch from each assigned state till arrival at a clock boundary,namely, at a state which is not an initial state, the information of anode which is not any of a loop, a conditional branch and a label branchobtained by the search is acquired, and the acquired information ismerged with the “retain” information of the variable table, thereby toextract a state machine for use in a HDL description. An example of astart state ST0 is shown in FIG. 54. Although the descriptions of statesare not especially restricted, codes are generated by the DFS from theindividual states. In this case, the codes are generated by bringingstate variables into the forms of “nxt_state=ST0”, etc.

Especially, regarding the variable to which the description “nxt_”hasbeen affixed by the “retain” information, the state machine for the HDLdescription is extracted using a variable name bearing the description“nxt_”, not the original variable name. Besides, the “&” operationbetween a signal and a constant has been used for the bit width analysisand has become unnecessary, so that it is deleted. Incidentally, theconstant is converted into the binary notation of HDL in considerationof the number of bits of the left hand of an input, so as to conform tothe HDL description.

In the acquisition of the “retain” information of the variable table,from among individual state transition columns, there are acquired allcolumns in which the same state as at the start of the depth-firstsearch is a start state, and it is identified whether the “retain”information depends only upon the start state or also upon an arrivalstate, or it depends upon the arrival state and a branch condition.Except in a case where the “retain” information depends only upon thestart state, the description “pred( )” of the “retain” information iscompared with the branch condition of the CFG, whereby an assignmentformula stored in the variable table is inserted into the appropriateposition of the HDL code as the “retain” information. Exemplified inFIG. 55 is a situation where the codes conforming to the “retain”information items are extracted from the variable table and are utilizedfor the extraction of the state machine.

Acquired examples of state machine descriptions conforming to the HDLdescription, in the start state ST0 are shown in FIGS. 54 and 55.Acquired examples of state machine descriptions conforming to the HDLdescription, in a start state ST1 are shown in FIGS. 56 and 57. Acquiredexamples of state machine descriptions conforming to the HDLdescription, in a start state ST2 are shown in FIGS. 58 and 59.

<<HDL Description Generation Process>>

In the HDL description generation process S6, a module declarationgenerates an HDL description which is obtained in such a way thatsymbols * expressive of a type and a pointer are deleted from a functiondeclaration in the C description as contains the circuit operationdescription part, and that descriptions “clk” and “reset_n” are added tothe resulting declaration. An input/output declaration is generated asan HDL description in such a way that a variable which is an argument inthe function declaration and which exists only at the left hand of anassignment formula is set as an output, while a variable which existsonly at the right hand of the assignment formula is set as an input, andthe bit width of the HDL description is identified by the methodexplained in the descriptive contents of the C description. A “reg”declaration is generated as an HDL description together with the “reg”specification statement of the descriptions “clk” and “reset_n”, in sucha way that variables finally left in the conversion processing thus farperformed, and variables added in the conversion processing thus farperformed are identified among the local variables stated in the Cdescription. The HDL description of the “wire” declaration of a variableallotted to a branch condition in the CFG generation process isgenerated, so as to generate an HDL description which contains theassignment statement of the branch condition for the allotted variable.Also, the HDL description of a parameter specification statement forexpressing an assigned state as a binary number is generated.

Besides, regarding register assignment statements, all the registerassignment statements and variable declarations at the right handsthereof are acquired. Ina case, for example, where the acquiredinformation items are:

-   unsigned char sig1_latched=0x00;-   unsigned char sig2_latched=0x00;-   unsigned short out;-   sig1_latched=$ sig1&0x03;-   sig2_latched=$ sig2&0x13;-   out=$ exe_result&0x1FFF;

the following HDL descriptions are generated: always @(posedge clk ornegedge reset_n) begin if (!reset_n) begin sig1_latched_o <= 2′b00;sig2_latched_o <= 3′b000; end else begin sig1_latched_o <=sig1_latched_i; sig2_latched_o <= sig2_latched_i; out_o <= out_i; endend

Subsequently, reference is had to the storage of a variable bearing thedescription “nxt_” as obtained in the state machine extraction part, andthe declaration part of the variable is acquired. In case of thisexample, “a_tmp” is pertinent, and the declaration part is:

-   unsigned short nxt_a_tmp=0x0000

At the generation of the “reg” declaration description, the effectivebit width has been known 15 bits from the assignment:

-   a_tmp=$ 0x7FFF&a

Therefore, the following description is generated: always @(posedge clkor reset_n) begin if (!reset_n) begin state = ST0; a_tmp =15′b000000000000000; end else begin state = nxt_state; a_tmp =nxt_a_tmp; end end

Besides, the HDL descriptions of the extracted state machines arejoined. For the left hands of the assignment statements in therespective states, statements are created in which correspondingvariables of “_o” are assigned to the variables of the left hands of theregister assignments and the variables added in the register assignmentstatement identifying part, while initial values are assigned to theother variables. Also, a statement “nxt_state=ST0” is created. Partscorresponding to the defaults of “case” statements are created, and theyare also joined. The variables of the right hands, and the variables of“wire” declaration are arrayed through “or”s, thereby to generate thefollowing description: Always @(state or c1 or c2 or valid_a_tmp_i orvalid_a_tmp_o or valid_a_tmp or a_tmp or valid_out_i or valid_out_o orout_i or out_o) begin case(state[1:0]) endcase endThe joined HDL descriptions are inserted between the “case” statements,and a description “endmodule” is affixed to the last line. Thus, the HDLdescription generation is completed. The Nos. of lines are merely added.

The HDL descriptions generated by the HDL description generation processS6 are exemplified in FIGS. 60 through 62.

According to the design method thus far elucidated, functions andadvantages to be stated below are attained.

Pseudo C descriptions in which clock boundaries are explicitly insertedinto C descriptions are input, thereby to realize parallel descriptionsof statement level based on register assignment statements, so that apipeline operation attended with a stall operation can be represented.

Since functions can be designed at a program level without caring aboutstate machines, the quantity of descriptions is decreased, so that thedesign method contributes, not only to shortening the term of adevelopment, but also to enhancing a quality.

Besides, it is permitted to describe a bus interface circuit and anarbitration circuit which cannot be represented by the generaldescriptions of program level as do not designate the clock boundaries.Especially, since register assignments are describable, descriptions canbe made in consideration of parallelism at the statement level, and acomplicated circuit operation such as the pipeline operation attendedwith the stall operation can be easily described with a smaller quantityof codes than in the C descriptions.

Besides, since the pseudo C descriptions are converted into the Cdescriptions which are compilable by a conventional C compiler, ahigh-speed simulation is realized, and the number of man-hour forverifying functions can be sharply diminished. In the function design,accordingly, sharp diminutions in the number of man-hour are realized inboth the logic design and the logic verification.

The design method is applicable to the development of, for example, acache controller or a DMA controller of which a cycle precision isrequired and for which a high-level synthetic tool is unsuitable, and itis greatly contributive to shortening the term of the design.

Although the invention made by the inventors has been concretelydescribed above in conjunction with the embodiments, the presentinvention is not restricted thereto, but it is, of course, variouslyalterable within a scope not departing from the purport thereof.

By way of example, the program descriptions and circuit descriptionsexplained before are merely exemplary, and they can be applied tovarious logic designs. The HDL is not always restricted to the RTL. Theprogram description language is not restricted to the C language, but itmay well be any other high-class language. Further, it is possible toemploy a virtual machine language such as “Java” (registered trademark).

The present invention is extensively applicable to the design of a CPUand the like logic circuits.

1. A compiler comprising: a conversion program, wherein the conversionprogram can convert first program descriptions described by diverting apredetermined program language into circuit descriptions, the firstprogram descriptions contain register assignment statements withparticular operators and clock boundary descriptions, and which permitcircuit operations to be specified at a cycle precision, and the circuitdescriptions specify hardware realizing the circuit operations specifiedby the first program descriptions in a predetermined hardwaredescription language.
 2. A compiler comprising: a conversion program,wherein the conversion program can convert first program descriptionsdescribed by diverting a predetermined program language can be convertedinto second program descriptions using a predetermined program language,the first program descriptions contain register assignment statementswith particular operators and clock boundary descriptions, and whichpermit circuit operations to be specified at a cycle precision, and thesecond program descriptions contain transformed assignment statementsinto which the register assignment statements are transformed in orderto make states of preceding cycles referable, and register assignmentdescription insertion statements which associate variables of thetransformed assignment statements with changes of registers attendantupon cycle changes, in correspondence with the clock boundarydescriptions.
 3. A compiler comprising: a conversion program, whereinthe conversion program can convert first program descriptions describedby diverting a predetermined program language into second programdescriptions using a predetermined program language, the first programdescriptions contain register assignment statements with particularoperators and clock boundary descriptions, and which permit circuitoperations to be specified at a cycle precision, the second programdescriptions contain transformed assignment statements into which theregister assignment statements are transformed in order to make statesof preceding cycles referable, and register assignment descriptioninsertion statements which associate variables of the transformedassignment statements with changes of registers attendant upon cyclechanges, in correspondence with the clock boundary descriptions, and thecircuit descriptions specify hardware which is defined by the secondprogram descriptions, in a predetermined hardware description language.4. The compiler of claim 1, wherein the predetermined program languageis a C language.
 5. The compiler of claim 1, wherein the hardwaredescription language is a description language of RTL level.
 6. A logiccircuit design method comprising: a first step; and a second step,wherein the first step inputs first program descriptions which containregister assignment statements and clock boundary descriptions bearingpeculiar operators, which are described by diverting a predeterminedprogram language in order to define circuit operations on the basis oftiming specifications, and which permit the circuit operations to bespecified at a cycle precision, and the second step generats circuitinformation which satisfies the timing specifications, on the basis ofthe first program descriptions.
 7. The logic circuit design method ofclaim 6, wherein the second step comprises the step of converting thefirst program descriptions, and generating as the circuit information,second program descriptions containing descriptions into which theregister assignment statements are transformed using input variables andoutput variables, and which assign the input variables to the outputvariables in correspondence with the clock boundary descriptions.
 8. Thelogic circuit design method of claim 7, wherein the second stepcomprises the step of converting the second program descriptions, andgenerating as the further circuit information, circuit descriptionswhich serve to specify hardware satisfying the timing specifications, ina predetermined hardware description language.
 9. The logic circuitdesign method of claim 8, wherein the program language is a C language.10. The logic circuit design method of claim 9, further comprising thethird step of performing a simulation of a circuit to-be-designed byemploying the second program descriptions.
 11. The logic circuit designmethod of claim 6, wherein the second step comprises the step ofconverting the first program descriptions, and generating as the circuitinformation, second program descriptions containing descriptions intowhich the register assignment statements are transformed using inputvariables and output variables.
 12. The logic circuit design method ofclaim 11, wherein the second step comprises the step of converting thesecond program descriptions, and generating as the circuit information,third program descriptions containing descriptions which assign theinput variables to the output variables in correspondence with the clockboundary descriptions, and being described in a predetermined programlanguage so as to be executable by a computer.
 13. The logic circuitdesign method of claim 12, further comprising the third step ofperforming a simulation of a circuit to-be-designed by employing thethird program descriptions.
 14. The logic circuit design methodcomprising: an input step; and conversion step, Wherein the input stepinputs first program descriptions which contain register assignmentstatements and clock boundary descriptions bearing peculiar operators,which are described by diverting a predetermined program language inorder to define circuit operations on the basis of timingspecifications, and which permit the circuit operations to be specifiedat a cycle precision, and the conversion step generates second programdescriptions containing descriptions into which the register assignmentstatements are transformed using input variables and output variablesand which assign the input variables to the output variable incorrespondence with the clock boundary descriptions, and being describedin the predetermined program language.
 15. The logic circuit designmethod of claim 14, wherein, in course of generating a CFG on the basisof the first program descriptions, the conversion step sets clockboundary nodes in the CFG in correspondence with the clock boundarydescriptions, whereupon it inserts the register assignment descriptionsbehind the clock boundary nodes.
 16. The logic circuit design method ofclaim 15, further comprising an optimization step of optimizing codes ofthe second program descriptions, while a variable table of respectivestate transitions is being created by utilizing the CFG.
 17. The logiccircuit design method of claim 16, further comprising a “retain” step ofextracting parts in which variables do not change between states withinthe variable table, as parts which need to be retained, and addingdescriptions for assigning the input variables to the output variables,to the extracted parts.
 18. The logic circuit design method of claim 17,further comprising an extraction step of extracting the codes whichconstitute state machines, on the basis of the variables and argumentsof the respective state transitions within the variable table havingundergone said “retain” step.
 19. The logic circuit design method ofclaim 18, further comprising the step of describing hardware of acircuit which satisfies the circuit specifications, in a predeterminedhardware description language, while reference is being had to the statemachine constituting codes extracted by said extraction step, and to thesecond program descriptions.
 20. The logic circuit design method ofclaim 14, wherein, whether or not a loop to be executed in the 0th cycleis existent is decided for the first program descriptions, and when theloop has been decided to be nonexistent, the step of describing hardwareof a circuit which satisfies the circuit specifications, in apredetermined hardware description language, is performed.